This invention relates to a current mode output circuit. More particularly, this invention relates to an output circuit with a discretely variable output current.
One type of data interface uses changes in the magnitude of a current to transmit data signals. In the simplest case, one state is represented by the presence of a current flow and another by the absence of current. An output circuit of this type using a switch S to connect a current driver through the output nodes to a load RL is shown in FIG. 1a. 
Other conventional data interfaces, such as those used in SCSI architecture, require a current to be always present on an active interface. The direction of current flow indicates whether the transmitted signal is a logic 0 or a logic 1. A conventional current steering output buffer of this type is illustrated in FIG. 1b. The circuit contains a current driver which is connected to the output nodes by a current switch. In a first state, switch pair SA is closed, switch pair SB is open, and the current driver contributes a current I to the total load current. In a second state, switch pair SB is closed, switch pair SA is open, and the current driver contributes a current of -I to the total load current. In conventional systems, current may be turned off by opening both switch pairs SA and SB.
As performance of integrated circuits continues to increase, the limited number of I/O (input/output) pins demands better utilization. Incorporating an output signal with more than the two conventional digital output states over a wire allows the interconnect of the I/O to carry a larger data bandwidth. Previous attempts to do this have used signalling via multiple voltage levels. However, in many circumstances, it is preferable to use current signaling instead. Further, conventional circuits generate switching noise at either of the power supply leads as the amount of power flowing into the output circuit is continuously changed to thereby vary the output signal level.
According to the present invention, an output buffer is provided that utilizes current signaling to provide a multi-level data output and draws a constant amount of current from the power supply regardless of the output level, thus reducing switching noise and startup delays. An output buffer circuit according to a first embodiment of the present invention has a current driver supplying a current I which is connectable to a load resistance. The connection may be through a current switch. The circuit also has one or more bypass resistors which can be switchable connected in parallel with the load resistance or disconnected from the circuit. When a bypass resistor is switched in parallel with the load resistor, some of the output current is diverted through the bypass resistor, thus reducing the current supplied to the load. For N switched bypass resistors, there are 2N possible resistor state combinations. By choosing appropriate resistance values for the bypass resistors, the current through the load resistor may be varied in 2N discrete. The number of states may be increased to 2N+1+1 if a current switch which allows the direction of the output current to be reversed or stopped is included in the output circuit. According to the invention, a zero-current output state is achieved by closing all switches in the current switch, instead of opening them. In this state, the introduced current flows equally in both directions through the load and therefore does not contribute a net current even though the given current driver is still sourcing current. Because the effect of a current driver on the load current may be eliminated without shutting off the current, it is possible to avoid startup delay and noise which would be introduced if the current switch were disconnected from the circuit by opening all the internal switches. Preferably, N bypass resistors are provided having appropriate resistances to provide at least N equal current steps for each current direction.
In another embodiment, a plurality of current drivers is provided and connected to the load resistance in parallel. It can be appreciated that when both of the current paths in a given current switch are active (e.g., all internal switches in a particular current switch are closed), no net current flow will be introduced into the load. However, the internal switches will also introduce a resistance in parallel with the load resistor. According to this aspect of the invention, the resistance of each internal switch is chosen so that when all internal switches are closed, the current switch provides a preselected effective resistance in parallel with the load which diverts current flow from other (active) current drivers and thereby reduces the current in the load by a predefined discrete amount. The magnitude of each current source and the effective resistance of the switches in each current switch can be chosen to minimize the number of redundant output states, and therefore maximize the number of possible output current steps.
A multiple-state current output circuit according to the present invention can be fabricated as an integrated circuit using MOS transistors and located on the same chip as its driving circuitry The present design allows for compact circuit dimensions when compared with conventional circuits of a similar type.